This invention generally relates to the formation of internal electrical connections in semiconductor integrated circuits and more particularly to internal bridging contacts formed at the submicrometer level insulated from an intervening conductive feature.
2. Description of the Prior Art
As the density of very large scale integrated, or VLSI, circuits continues to increase, the formation of features and electrical connections between such features becomes more difficult. I and others in U.S. Pat. No. 4,832,789 and IEEE Proceedings V-MIC Conference, pp. 95-100, Jun. 13-14, 1988, have disclosed techniques which include an approach for forming a self-aligning internal interconnecting bridging contact which may be used at the submicrometer level.
The disclosed approach creates a shallow trench and connecting passageways. The passageways extend through layers of the VLSI circuit to contact points on the surface of a substrate. The trench and passageways are filled with metal to form a bridging contact between the contact points. This approach may be utilized to connect conductive runners or other contact points separated by intervening conductive features, such as a transverse runner. In this disclosed approach, a dielectric is deposited on the substrate covering all the runners, two passageways connected by a shallow trench are etched through the dielectric to the runners to be connected, and metal is deposited into the passageways and trench completing the bridging contact.
In particular, the dielectric layer is deposited on the substrate followed by an etch stop layer deposited on the dielectric layer. A layer of photoresist is applied to the etch stop layer, exposed in a predetermined pattern and developed. After removal of the unexposed photoresist, a photoresist pattern remains on the etch stop above the runners to be connected. The photoresist pattern is then etched away together with the exposed etch stop and a portion of the dielectric to form a trench in the dielectric, positioned over and larger in width than the transverse runner. Another layer of photoresist is then applied and patterned in the trench over an area only slightly larger than the transverse runner.
A second etching removes the remaining exposed portions of the trench down to the substrate, creating two passageways to the runners to be connected, while leaving dielectric over and around the transverse runner. The trench and passageways are filled with metal to form a bridging contact between the runners without contacting the transverse runner. Excess metal above the surface of the trench and the remainder of the etch stop layer is then etched to form a planarized surface with the dielectric, if desired.
One benefit of this known approach is that the passageways are self-aligning with the runners to be connected. However, it is difficult to sufficientiy and accurately control the etching process to leave an adequate amount of dielectric over and around the transverse runner to act as an insulator. Too short an etch will not expose the runners to be connected while too long an etch will expose the transverse runner. It is also difficult to apply and pattern photoresist in the trench. The lithographic process used to pattern photoresist does not always work well in such small subsurface areas, particularly in areas with high aspect ratios.
What is needed is a technique which retains the self-aligning feature, and many of the other advantages of my former approach, while providing improved control over the second etching process. The needed technique must reliably expose runners or other contact points on the substrate while avoiding the inadvertent exposure of any intervening features. In addition, the technique should avoid the need to pattern photoresist in non planar features and/or at subsurface levels.